The demand for electrically erasable and programmable non-volatile memory devices continues to increase in their applications. High capacity non-volatile memory devices are particularly advantageous because of successive developments with Riger frequencies and improved integration density.
Several technologies exist to embed a plurality of non-volatile memory devices on one chip. Doping so enhances data storage capacity for digital multimedia such as an SSD (Solid State Disk) and expansion memory cards.
FIG. 1 illustrates a conventional multiple chip memory system including a conventional multiple chip. Referring to FIG. 1, a first chip 102 and a second chip 104 are included in a multiple chip 100. A host 110 and the multi-chip 100 are connected through control signals CNT, ready/busy signals R/B1 and R/B2, an input/output bus I/O BUS, and chip enable signals CE1 and CE2. The first chip enable signal CE1 selects the first chip 102 and the second chip enable signal CE2 selects the second chip 104. The ready/busy signals R/B1 and R/B2 arise respectively from the first chip 102 and the second chip 104. The R/B1 signal indicates a ready or busy state of the first chip 102. The R/B2 signal indicates a ready or busy state of the second chip 104. The r/B1 and R/B2 signals merge into a single ready/busy signal R/B provided to the host 110. FIG. 2 is a timing diagram of the system 100 shown in FIG. 1.
Referring to FIG. 2, a setup command of a memory system and address corresponding to the first and second chips are introduced into the memory system before data is loaded on the input/output bus I/O BUS. Data assigned to the first and second chips are inputted: data such as DATA10, DATA11 and DATA12 correspond to the first chip; and data such as DATA20, DATA21 and DATA22 correspond to the second chip. For example, it is assumed that the data from DATA 10 through DATA22, which are loaded into the input/output bus I/O BUS, are programmed in the first and second chips 102 and 104 of FIG. 1, respectively. In this case, the R/B1 signal has periods BUSY_, BUSY_11 and BUSY_12, which are activated to a low level until the data DATA10, DATA11 and DATA12, respectively are fully programmed in the first chip 102. Accordingly, if each of the R/B1 signal and R/B2 signals is low, the R/B signal is also low. A low level R/B signal indicates to the host 110 that the chip 110 cannot perform other commands because it is busy.
Even though the first chip 102 is ready to receive other commands after completing a cycle, it does not because the R/B signal indicates it is busy. A solution would be to hold the chip 102 on a standby state during a tloss time until R/B2 is high. The tloss period deteriorates system performance.
Accordingly, a need remains for a multiple chip system capable of improved performance.